Log inSign up free
  • Home
  • Profile
  • Jobs
    • Applications
    • Career
    • Resume
    • Cover letters
  • Content
    • Posts
    • Media
  • Messages
  • Analytics
    • Overview
    • Pages
    • Events
  • Portfolio
  • More tools
    • Hiring
  • Settings
All jobs
ALAstera Labs logo

Astera Labs

Singapore, Singapore

Analog Mixed Signal Design Engineer.

ENGINEERING

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

  • Pursuing a Master’s or PhD degree in EE is preferred

Desired Experience:

  • Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
  • Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
  • Solid track-record for implementation of analog circuits high-speed data transmission.
  • Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must
  • Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
  • Knowledge of TIA design and drivers for optical applications is highly desirable
  • Experience in RFIC design for wireless or wireline communication systems is highly desirable.
  • Strong technical independent contributor with a proven ability to drive results.
  • Excellent teamwork, presentation, and documentation skills.
  • Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
  • Strong experience in lab chip bring-up and debugging efforts.
  • Relevant research publications and/or patents in analog or RF IC design.
  • Familiarity in programming/scripting languages such as Python, Matlab, or C.
  • Experience with PCB design.
  • Familiarity with Verilog RTL or DSP design concepts.
  • Knowledge of optical transceivers.
  • Expertise in ESD protection techniques and IC packaging methodologies.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Pay
Not stated
Where
Singapore, Singapore
Work
Not stated
Type
Not stated
Posted
13 Oct, 2026
Apply on the original postingSign in to prepare an application

Verified board

more at Astera Labs.

13 Oct, 2026

Astera Labs

Tech Lead Analog Mixed-Signal IC Layout Engineer

ALAstera Labs logo
  • Lead
  • Engineering

Singapore, Singapore

Salary not listed

Details
13 Oct, 2026

Astera Labs

Teach Lead Physical Design Engineer

ALAstera Labs logo
  • Lead
  • Engineering

Singapore, Singapore

Salary not listed

Details
13 Oct, 2026

Astera Labs

Senior Manager, Global Safety & Security

ALAstera Labs logo
  • Lead
  • Security

$180k–230k/yr

San Jose +2

Details

similar roles.

1 Oct, 2026

YugabyteDB

Software Engineer II

YUYugabyteDB logo
  • Engineering

$150k–170k/yr

Sunnyvale, CA

Details
11 Aug, 2026

NavVis

Team Lead, System Software/UI - Embedded Linux, ROS, C++ (F/M/D)

NANavVis logo
  • Lead
  • Hybrid
  • Engineering

Munich Hybrid (NavVis GmbH)

Hybrid

Details
28 Sep, 2026

NavVis

Software Engineer SLAM (F/M/D)

NANavVis logo
  • Hybrid
  • Engineering

Munich Hybrid (NavVis GmbH)

Hybrid

Details
27 Apr, 2026

NavVis

Senior Software Engineer Android (Kotlin) (F/M/D)

NANavVis logo
  • Senior level
  • Hybrid
  • Engineering

Munich Hybrid (NavVis GmbH)

Hybrid

Details
16 Mar, 2026

NavVis

Senior Software Engineer, 3D Perception (C++ and Python) (F/M/D)

NANavVis logo
  • Senior level
  • On-site
  • Engineering

Munich Onsite (NavVis GmbH)

On-site

Details
5 Aug, 2026

NavVis

Senior Full Stack Software Engineer - Angular/Typescript/Python + Robotics Backend (F/M/D)

NANavVis logo
  • Senior level
  • Hybrid
  • Engineering

Munich Hybrid (NavVis GmbH)

Hybrid

Details