We are looking for a motivated and hands-on Physical Design Engineer to join our ASIC team. The ideal candidate should have strong fundamentals in Physical Design and Timing Closure, a passion for solving implementation challenges, and a willingness to learn and grow in a fast-paced startup environment.
This role offers the opportunity to work across multiple aspects of backend implementation, including floorplanning, placement, CTS, routing, timing closure, power optimization, and physical signoff, while collaborating closely with experienced engineers across the ASIC development flow.
Key Responsibilities
Physical Design Implementation
• Participate in block-level and subsystem-level implementation from netlist to GDS.
• Perform floorplanning, placement, CTS, routing, and physical optimization activities.
• Analyze and resolve timing, congestion, utilization, and routing issues.
• Support ECO implementation and timing closure activities.
Timing Analysis & Closure
• Perform setup and hold timing analysis using PrimeTime or equivalent STA tools.
• Debug timing violations and work with design teams to identify and implement solutions.
• Analyze clock quality, timing margins, and constraint issues.
Physical Verification & Signoff
• Support DRC, LVS, ERC, Antenna, and density closure activities.
• Work with Calibre and/or ICV to analyze and resolve physical verification issues.
• Assist in signoff checks and tapeout readiness activities.
Power & PPA Optimization
• Analyze power, performance, and area tradeoffs.
• Support leakage reduction, clock optimization, and power recovery activities.
• Assist in implementing low-power design techniques and optimization strategies.
Automation & Productivity
• Develop and maintain Tcl/Python scripts to improve flow efficiency and automate repetitive tasks.
• Contribute to flow improvements and engineering productivity initiatives.
Collaboration
• Work closely with RTL, DFT, DV, and Physical Design teams to support successful project execution.
• Participate in design reviews and technical discussions.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 2–5 years of ASIC Physical Design experience.
• Experience with at least one successful tapeout or advanced-stage implementation project.
Hands-On Experience In
• Floorplanning
• Placement and Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• ECO Implementation
• Physical Verification
EDA Tools
• Cadence Innovus
• Synopsys ICC2
• PrimeTime / Tempus
• Calibre / ICV
Scripting Skills
• Tcl scripting (required)
• Python scripting (preferred)
What We Are Looking For
• Strong hands-on Physical Design skills and solid backend fundamentals.
• Excellent debugging and problem-solving abilities.
• Curiosity to understand root causes rather than simply following existing flows.
• Willingness to take ownership of tasks and drive them to completion.
• Strong communication and teamwork skills.
• Ability to thrive in a fast-paced startup environment and adapt to evolving priorities.
All your information will be kept confidential according to EEO guidelines.