๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฏ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฒ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฏ๐ฑ-๐ฒ๐ฌ ๐๐ฃ๐)
Experience: 7+ yrs
Location: Bengaluru
Job Type: Full-time
We are looking for an experiencedย Senior Design Verification Engineerย with strong expertise inย SystemVerilog (SV) and UVM-based verificationย to drive verification activities for complex IP and SoC designs.
The ideal candidate will have hands-on experience executing multipleย IP and SoC verification projects, developing robust verification environments, creating verification plans, debugging functional and gate-level simulations, and driving coverage closure. Experience with at least one industry-standard protocol such asย Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDRย is required.
Requirements
Key Responsibilities
- Develop and execute comprehensiveย design verification strategies and plansย for IP and SoC projects.
- Translate functional and technical requirements into detailedย verification plans, test scenarios, and coverage objectives.
- Develop scalable and reusableย SystemVerilog/UVM verification environments.
- Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models.
- Set up, configure, execute, and debugย functional and gate-level simulations.
- Develop and maintain automated regression environments for large verification programs.
- Analyze simulation failures, identify root causes, and collaborate with RTL and design teams to resolve issues.
- Verify designs using industry-standard protocols such asย Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or equivalent protocols.
- Evaluate, integrate, configure, and validateย third-party Verification IP (VIP).
- Develop effective test strategies for functional, corner-case, error, and protocol-specific scenarios.
- Performย functional and code coverage analysisย and drive coverage closure.
- Identify verification gaps and develop additional tests, assertions, or coverage models where required.
- Review simulation results, regression trends, coverage reports, and verification metrics.
- Improve verification infrastructure, methodologies, automation, and regression efficiency.
- Collaborate with RTL, architecture, firmware, emulation, and other engineering teams throughout the verification lifecycle.
- Participate in design and verification reviews and contribute technical recommendations.
- Maintain verification documentation, test plans, environments, results, and closure reports.
- Mentor junior verification engineers and contribute to verification best practices and methodology improvements.
What Makes You a Great Fit
- 7+ years of professional experienceย in ASIC, SoC, IP, or semiconductor design verification.
- Proven experience executingย at least 3 IP or SoC verification projectsย from planning through verification closure.
- Strong hands-on expertise inย SystemVerilog and UVM methodology.
- Experience developing and maintaining reusable UVM-based verification environments.
- Strong experience translating functional requirements intoย verification plans and test strategies.
- Hands-on experience setting up and debuggingย functional and/or gate-level simulations.
- Strong experience developing verification environments and automatedย regression setups.
- Practical experience withย functional coverage, code coverage, coverage analysis, and coverage closure.
- Experience evaluating and integratingย third-party VIPsย into verification environments.
- Strong understanding of digital design, RTL concepts, simulation, debugging, and verification methodologies.
- Hands-on experience with at least one industry-standard protocol such asย Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR.
- Strong debugging, analytical, and problem-solving capabilities.
- Ability to investigate complex simulation failures and identify root causes across RTL, testbench, and verification environments.
- Experience with industry-standard simulators and verification tools is desirable.
- Strong scripting or automation skills using languages such asย Python, Perl, or Tclย are an advantage.
- Excellent communication and collaboration skills with the ability to work effectively across design and verification teams.
- Strong ownership mindset with the ability to independently drive verification activities fromย planning through coverage closure.