Meet the team Join our dynamic Test Timing Engineering team, a group of passionate experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs. Our work is critical to the success of the broader silicon design process, enabling efficient test and verification of complex integrated circuits. The team is mid-sized, blending seasoned engineers with fresh perspectives, fostering a collaborative and supportive environment. You’ll find an atmosphere of innovation, continuous learning, and strong cross-functional collaboration, all driven by a commitment to technical excellence. If you thrive on solving challenging problems and making a tangible impact on product quality, you’ll feel right at home here. Your impact As a Test Timing Engineer, you will play a pivotal role in developing and validating timing constraints that ensure the accuracy and reliability of advanced chip designs. Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes. Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis. Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows. Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution. Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all design stages. Minimum qualifications Bachelor’s degree in electrical or computer engineering (or equivalent field) with 8+ years of relevant work experience or Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience. Demonstrated experience developing block/full-chip SDC in test modes (scan shift, scan capture, ATPG capture). Proficiency in Static Timing Analysis (STA) and hands-on experience with tools such as PrimeTime. Programming proficiency in at least two scripting languages (e.g., Perl, TCL, Python, Makefile). Proven track record in SDC validation, timing exception handling, and STA flow development. Preferred qualifications Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience. Experience debugging and analyzing timing constraints for DFT modes (scan shift/capture, BIST) Prior hands-on experience with SDC debugging and STA tools (Synopsys GCA/TCM/PrimeTime) Experience with synthesis tools, especially Synopsys Fusion Compiler, and Tessent DFT insertion Strong communication skills and proven ability to work collaboratively within cross-functional teams Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds bring when we work together. Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life’s best work.

Senior STA Timing Engineer.

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