Our client is a global technology provider operating in the automotive industry. It develops software, electronic systems and advanced technologies for vehicle safety, connectivity and automated driving. This opportunity is within its Research & Development (R&D) centre, where engineering teams develop next-generation automotive solutions.
Your tasks:
As Senior ASIC Analog/Mixed-Signal Verification Engineer you create models and verification tests of an ASIC in our Advanced Electronics & Semiconductor Solutions (AESS) department in Timisoara.
You have the opportunity to work on AUMOVIO’s diverse innovative automotive applications and find optimized solutions for their specific needs.
The stringent automotive requirements are to be met during verification process.
Your tasks include
Develop the mixed-signal verification strategy and its related test bench
Create models for analog blocks to be used in mixed-signal verification
Build block and system-level test benches and verification environments using Verilog/Verilog-A/SystemVerilog
Construct support utilities for verification automation, test bench automation, and other verification enhancements to improve productivity
Mentor the team and provide technical support for modelling and verification activities
Support the development of verification test plans, and verification activities
Contribute to verification infrastructure development for complex ASICs
Formulate test plans based on functional requirements, applicable standards requirements
Responsible for the definition, development, and execution of self-checking tests
Contribute to the post-silicon validation of ASICs in the lab, writing tests and scripts
Your profile
Master of Science / PhD in Electrical Engineering / Microelectronics / Physics or similar
5+ years of relevant verification experience in analog mixed-signal circuits
Understanding of design of analog circuit
Excellent programming skills on Verilog, SystemVerilog, VerilogAMS and Verilog-A
Experience in script programming(Perl/Python/Makefile/Shell and ) would be a plus
Testbench development for the verification of Mixed-Signal blocks using SystemVerilog
Familiarity with best practice chip-level verification techniques and languages
Experience with CAD Tools (ideally, Cadence AMS Simulation environment)
Familiar with usage and creation of interface elements for mixed signal simulation
Very good English language skills written and spoken
Planning and organizing skills, ability to take initiative and to communicate effectively, eagerness to grow and develop