Job Details: Job Description: Be a part of Intel's Advanced Packaging Command Center (APCC), the global command center for Advanced Packaging that provides remote capabilities, follow-on engineering, and operational support across Wafer Packaging Manufacturing (WPM). Through APCC, engineering expertise is focused to improve coordination across regions, drive standardization, and improve responsiveness, while strengthening end-to-end operational execution across regions and delivering consistent, high-quality execution at scale. As the defect review technician, you will be instrumental in supporting global defect review activities, including defect classification, validation, and hold lot disposition. You will help maintain quality excellence while contributing to APCC's mission of delivering standardized, high-quality execution at scale. Your primary focus will be the accurate classification of defects captured by multiple inspection systems. Through precise defect classification, you will play a vital role in minimizing defect noise, driving systematic defect reduction initiatives, and maintaining the optimal balance between quality control and manufacturing efficiency. Responsibilities will include but are not limited to Defect Classification and Analysis: • Review and Analyze defect images captured by diverse metrology tools. • Accurately classify defects based on documented defect specification. • Distinguish between true defects requiring disposition action and false positives or nuisance defects. • Maintain proficiency across multiple inspection platforms and adapt classification criteria to different tool capabilities and imaging conditions Defect Validation: • Verify defect classifications against established criteria and specifications • Partner with Layer Owner to ensure consistent defect categorization approaches • Prevent over-rejection scenarios by accurately identifying non-critical defects and cosmetic variations that do not impact product performance. • Avoid under-rejection situations by ensuring killed defects are properly identified and flagged for disposition. Hold Lot Disposition: • Ensure strict compliance in review and disposition of hold lots based on documented Out-of-Control Action Plans (OCAP) • Ensure proper documentation and traceability of all disposition decisions. • Collaborate with Layer Owner to update and refine OCAP procedures based on emerging defect patterns • First Level Defect Analysis • Perform comprehensive first level defect analysis as the initial point of technical review for all flagged defects. • Document initial findings and recommendations to support Layer Owner analysis and decision-making processes. Qualifications: Minimum qualifications are required to be initially considered for this position. • Diploma in Engineering (Manufacturing, Mechatronics, Semiconductor Technology, Electronics, Mechanical or related disciplines), Diploma in Science Stream (Computer Science, Information Technology (IT), Physics, Chemistry, Mathematics & Statistics or related disciplines) • 1+ years of working experience in semiconductor manufacturing, wafer fabrication, advanced packaging, metrology, inspection, quality, or manufacturing operations environments. • Ability to work rotating shifts to provide continuous support across global manufacturing operations. • Strong English communication skills, including reading, writing, and verbal communication. • Proficiency in computer-based work and ability to maintain focus and accuracy while reviewing large volumes of inspection images. • Ability to work at a workstation for extended periods while maintaining attention to detail and review quality. Preferred Qualifications: • Experience with defect classification, image review, defect inspection systems, or manufacturing quality processes is an added advantage. • High attention to detail and commitment to quality standards. • Effective communication and teamwork skills in a global, cross-functional environment. • Willingness to learn new technologies, inspection platforms, and manufacturing processes. We invite you to bring your technical expertise, curiosity, and passion for innovation to Intel, where you will have the opportunity to contribute to groundbreaking technologies and shape the future of semiconductor manufacturing. Job Type: Experienced Hire Shift: Shift 9 A1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process

Defect Review Technician.

more at Intel.

CPU Performance Architect

GPU Logic Design Engineer

Signal Integrity Engineer

similar roles.

Sr. Applications Developer

PowerBuilder Developer

Principal Product Developer, Population Health Strategy

People Partner Director, Engineering (REMOTE US- West Coast Preferred)

Partner Solution Architect - SAI

Forward Deployed Engineer III - IN (Palantir)