Log inSign up free
  • Home
  • Profile
  • Jobs
    • Applications
    • Career
    • Resume
    • Cover letters
  • Content
    • Posts
    • Media
  • Messages
  • Analytics
    • Overview
    • Pages
  • Portfolio
  • Builder
  • More tools
    • Hiring
  • Settings
All jobs
INIntel logo

Intel

SRR4 - SRR4 - Sarjapur 4, India

GPU Logic Design Engineer.

ENGINEERING
Job Details: Job Description: The Role and Impact : As a GPU Logic Design Engineer, you will play a pivotal role in developing and optimizing the RTL design for cutting-edge graphics IPs, including compute, display, and media components. On a day-to-day basis, you will create logic designs, write RTL code, and conduct simulations to ensure high-quality integration of GPU blocks within full chip designs. By contributing to architecture definition and microarchitecture features, your work will directly impact Intel's ability to deliver state-of-the-art performance in graphics hardware. The candidate will also be responsible for Verifying the designs on their own or with other team members, including, test plan, TB changes, test content, debug, coverage etc. Business Group: The role is part of Intel's Data Center Group (DCG), which focuses on advancing high-performance computing solutions that power data centers around the world. This group develops innovative GPU hardware designs that enable Intel's leadership in graphics and compute technologies, supporting scalable solutions for data-intensive workloads. DCG drives the creation of solutions that amplify Intel's broader mission of powering a data-driven future. Key Responsibilities: - Develop logic design, RTL coding, and simulation for GPU IPs, including graphics and media components. - Collaborate on defining architecture and microarchitecture features of the designed blocks. - Optimize logic for power, performance, area, and timing to meet design goals. - Review and implement verification plans to ensure correctness across validation hierarchies. - Resolve and implement corrective measures for RTL tests to guarantee feature integrity. - Support SoC customers for seamless GPU block integration in chip designs. Qualifications: Minimum Qualifications : - Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field. - 6+ years of hands-on experience in IP RTL design, with demonstrated skills in microarchitecture and system verification using Verilog/SystemVerilog. - Proficiency in logic design optimization, timing analysis, and validation workflows. - Experience in scripting languages such as Python or Perl for automation purposes. - Knowledge of computer architecture and basic digital electronics principles. Preferred Qualifications: - Master's degree in a relevant field with 6+ years of industry experience or PhD with no prior professional experience. - Familiarity with UVM concepts and developing testbenches, monitors, and scoreboards. - Strong problem-solving skills and debugging capabilities for complex design challenges. - Effective collaboration and communication skills to work in cross-functional teams. Take the next step in advancing the future of GPU hardware innovation-apply now to be part of Intel's groundbreaking team where your contributions will shape the evolution of graphics technology. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process
Pay
Not stated
Where
SRR4 - SRR4 - Sarjapur 4, India
Work
Not stated
Type
Not stated
Posted
23 Oct, 2026
Apply on the original postingSign in to apply

Verified board

more at Intel.

28 Oct, 2026

Intel

CPU Performance Architect

INIntel logo
  • Senior level
  • Engineering

India, Bangalore

Salary not listed

Details
28 Oct, 2026

Intel

GPU Logic Design Engineer

INIntel logo
  • Engineering

India, Bangalore

Salary not listed

Details
28 Oct, 2026

Intel

Signal Integrity Engineer

INIntel logo
  • Engineering

India, Bangalore

Salary not listed

Details

similar roles.

28 Oct, 2026

Flow Traders

Senior Software Engineer - Post-Trade Platform

FTFlow Traders logo
  • Senior level
  • Engineering

Amsterdam

Salary not listed

Details
26 Oct, 2026

Flow Traders

Senior Software Engineer - OTC Trading

FTFlow Traders logo
  • Senior level
  • Engineering

Amsterdam

Salary not listed

Details
27 Oct, 2026

Sonos

Mechanical Engineer

SOSonos logo
  • Engineering

Shenzhen – Sonos Shenzhen Branch, China

Salary not listed

Details
28 Oct, 2026

Sonos

Software Product Management Intern (Seattle)

SOSonos logo
  • Internship
  • Intern
  • Engineering

Seattle, United States of America

Internship

Details
26 Oct, 2026

Maricopa

Transportation Standards Engineer

MAMaricopa logo
  • Engineering

$90k–111.9k/yr

MCDOT Administration Phoenix, United States of America

Details
28 Oct, 2026

Fina

Stagiaire Engineering

FIFina logo
  • Intern
  • Engineering

Paris La Défense, France

Salary not listed

Details