Business Line Description: NXP's MPU Engineering (ACE) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide-range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly-integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards. We are seeking an experienced Digital Designer for Physical Design for advanced semiconductor products. This role will own end-to-end physical design execution across complex designs, driving delivery from RTL to silicon for cutting-edge technology nodes. The ideal candidate demonstrates deep technical expertise to implement a given design on silicon with optimized quality and meeting PPA targets. Key Responsibilities 1. End-to-End Physical Design Ownership Lead Physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff. Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness. Deliver optimized PPA (Power, Performance, Area) across complex designs. Aligns with internal expectations of implementing designs on silicon with optimal quality, PPA, and cost efficiency 2. Team Leadership & Organization Development Participate in mentoring and career development. Role-Model execution discipline, review mechanisms, and performance tracking. Interface with senior leadership for status reporting, escalation, and decision-making. 3. Technical Strategy & Innovation Define and deploy next-generation physical design methodologies. Drive automation, flow optimization, and tool innovation. Lead adoption of advanced node technologies (5nm and beyond). Improve scalability, productivity, and design quality through methodology enhancements. 4. Cross-Functional & Ecosystem Engagement Collaborate with architecture, RTL, verification, and product teams to ensure design convergence. Interface with EDA vendors and IP providers for tool and flow optimization. Support post-silicon bring-up, yield improvement, and production ramp activities. Core Technical Expertise Full RTL-to-GDSII implementation flow (Cadence and/or Synopsys tool sets) Floorplanning, synthesis, PNR, CTS, routing STA and signoff methodologies Physical verification (DRC/LVS/ERC) Advanced node implementation (≤ 16nm / 5nm) Low power design (UPF/CLP) Scripting in Python, TCL, and Perl Required Qualifications Bachelor’s or Master’s in Electrical / Electronics Engineering or related field 10+ years of experience in ASIC / SoC physical design Strong knowledge of industry EDA tools (Synopsys, Cadence flows) Strong communication skills Preferred Qualifications Experience in high-reliability SoCs Exposure to AI-driven design methodologies and automation Why This Role Matters Own delivery of flagship SoCs at advanced nodes Drive innovation in physical design methodologies Direct impact on silicon success and product competitiveness More information about NXP in India... #LI-2734 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Are you already an NXP employee? Do not apply here. Instead, you must apply via our internal career page. Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

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